The present invention relates to electronic circuits and the field of frequency modulation circuits. More particularly, the present invention relates to a circuit which finely controls the frequency spectrum of a clock signal.
The demand for today's high-speed electronic equipment has created a number of problems for circuit designers and manufacturers. The high-speed electronic equipment require clocks operating at higher frequencies. The higher frequencies, in turn, increase the level of electromagnetic interference (EMI). In addition, long traces of wire on printed circuit boards further add to the EMI levels. The increased levels of EMI can negatively effect the operation of components in proximity to such high-speed circuitry due to the coupling of the radiated energy. Therefore, it is desirable to lower the unwanted EMI energy levels while increasing the speed of the electronic circuitry.
In the United States, the Federal Communications Commission (FCC) has established rules and standards regarding EMI emissions from electronic equipment. The FCC emission limitations are published in the Code of Federal Regulations. FCC also enforces these standards and levies fines against violators. Compliance with the FCC standards has become quite a challenge for most circuit board manufacturers. To add to the problem, consumers increasingly demand higher performance from the products they purchase.
One solution is to attempt to filter the high EMI emission signals. However, filtering signals at such high speeds is not practical because it tends to degrade the performance of the system. An additional solution is to utilize metal shielding to reduce the EMI levels. This solution is also impractical because it is prohibitively expensive.
Another solution used for reducing the peak energy of a clock signal is frequency modulation. FIG. 1 illustrates the energy levels of an exemplary clock signal concentrated at its fundamental frequency. A signal 102 illustrates the energy level of the clock signal at its fundamental frequency of 100 MHz. The FCC energy limit is illustrated by line 104. Signals 106 and 108 represent the energy levels of the clock signal at its third harmonic frequency of 300 MHz and fifth harmonic frequency of 500 MHz, respectively. As shown, the peak energy level at the fundamental frequency 102 is very close to the FCC limit 104.
FIG. 2 illustrates the energy levels of a frequency modulated version of the clock signal shown in FIG. 1. A signal 202 illustrates the frequency modulated version of signal 102 of FIG. 1. As illustrated, signal 202 is modulated between a value of 99 MHz and 101 MHz. The FCC energy limit is illustrated by line 204. Signals 206 and 208 illustrate the energy levels of the modulated clock signal at its third harmonic of 300 MHz and fifth harmonic of 500 MHz, respectively. As shown, signal 206 is modulated between 297 MHz and 303 MHz. Signal 208 is modulated between 495 MHz and 505 MHz.
When a clock signal is frequency modulated, its spectrum is spread over a broader frequency band. As a result, this technique reduces the peak energy level of the signal. This advantage is clearly demonstrated by comparing FIGS. 1 and 2. For example, the peak energy level of the frequency modulated version of signal 102, illustrated as signal 202 in FIG. 2, is much lower than the peak energy level of the unprocessed signal 102. As a result, frequency modulation can more readily provide compliance with the FCC requirements. In fact, in certain applications where the peak energy levels of a clock signal already surpasses the FCC limits, frequency modulation can lower these levels sufficiently to avoid violating the regulations. Therefore, frequency modulation is capable of rendering certain legally unusable circuits employable by lowering the generated EMI levels.
Moreover, the frequency modulation has to be finely tuned. Otherwise, the resulting signal will be too far from the center frequency of the original signal. If this frequency excursion is not finely controlled, the recipient circuitry can be rendered inoperable for timing reasons.
Currently, phase-locked loop (PLL) circuits are used to provide precise clock signals in a variety of applications in the electronics field. The operation of the conventional PLL is well known in the art and will not be discussed in detail herein.
FIG. 3 illustrates a conventional PLL 300. A reference input signal (Fref) is received by the PLL 300 at an input node 302. A signal divider 304 divides the input signal by a factor M and provides the divided signal at a node 306. The signal divider 304 generates an output pulse for every M input pulses. A phase/frequency detector 308 compares the phase and/or frequency of the divided signal 306 with a feedback signal provided at node 310. Outputs of the phase/frequency detector 308 are connected to a charge pump 312. The charge pump 312 includes two current source devices 313 and 314 connected in series between a voltage source 315 and a ground 316. The charge pump 312 provides a signal on node 317 to a loop filter 318 based on the phase/frequency detector 308 outputs. The loop filter 318 includes a resistor 319 and a capacitor 320 connected in series between the charge pump output node 317 and a ground potential 322. The loop filter filters the charge pump output 317 in accordance with the selected values for the resistor 319 and the capacitor 320.
The charge pump output node 317 is also connected to a voltage controlled oscillator (VCO) 324. The VCO 324 provides an output on node 326 based on the voltage value of its input signal 317 which is provided by the charge pump 312, and filtered by the loop filter 318. The output of the VCO 324 is also connected to a second signal divider 328. The second signal divider 328 is configured to divide the VCO output signal 326 by a factor N. Hence, the signal divider 328 generates an output pulse for every N input pulses. The output of the second signal divider 328 provides the feedback signal on node 310 to the phase/frequency detector 308.
As a result, the PLL 300 will provide an output at node 326 with a frequency which is equal to the frequency of its input at node 302 multiplied by a factor N/M. Also, the PLL output 326 will have the same phase as the PLL input 302 because the phase/frequency detector 308 detects any phase differences between the divided signal 306 and the feedback signal 310 to provide a correction accordingly. The PLL 300, however, can only provide a precise output signal and is unable to provide a finely controlled frequency modulated signal.
From the foregoing, it will be understood that a method and circuit for finely controlling the frequency of a clock signal is desired which will minimize the EMI levels of the clock signal, particularly for high-speed electronic equipment utilizing a higher frequency for synchronization.